Cadence Design Systems (NASDAQ:CDNS) CEO Anirudh Devgan outlined how the company is positioning its electronic design automation (EDA), hardware, and intellectual property (IP) businesses around what he described as a “three-layer cake” of AI, physics-based “ground truth,” and accelerated compute and data. Speaking at an event in San Francisco, Devgan said the approach applies broadly across markets and is increasingly relevant as AI expands from data-center software into physical systems such as robots, cars, and drones.
Devgan’s “three-layer cake” and the next phase of AI
Devgan framed current AI development as a stack in which “AI at the top” runs on a middle layer of scientific and physics-based modeling, supported by compute and data at the bottom. He argued this combination is necessary across industries, with the “slice” varying by domain. In chip design, he said, the physics layer remains critical because advanced-node design requires high accuracy.
- Data-center AI deployed in software, which he characterized as the current phase.
- Physical AI (cars, robots, drones), which he expects to be a large next phase.
- Science AI (life sciences and materials), which he described as another major category.
In the Physical AI slice, Devgan said the dominant model shifts from large language models (LLMs) to “world models,” which require accurate simulated and synthetic data rather than relying on internet-scale text data.
Physical AI and the “sim-to-real” opportunity
Devgan highlighted the “sim-to-real gap” as a key challenge in Physical AI. He said world models require data that is difficult to capture through sensors at scale, making simulation essential—provided it is accurate enough to translate into real-world performance.
To address this, Devgan pointed to Cadence’s acquisition of Hexagon’s simulation business, describing its robotic simulation capability—specifically Adams—as “the most accurate robotic simulator.” He said Cadence plans to place Adams “in that loop” to improve simulation accuracy for Physical AI applications.
He added that silicon requirements also differ between data-center AI and Physical AI, with the latter emphasizing mixed-signal and low-power design. Devgan said this aligns with Cadence’s strengths given its history supporting automotive and embedded chip development, and he cited OEMs designing their own chips such as Tesla, Rivian, and BYD.
AI as “amplification,” plus ChipStack Super Agent
Addressing concerns about AI-driven volatility in software business models, Devgan said AI should be viewed as “amplification” rather than disruption for Cadence. He argued that higher efficiency does not reduce EDA usage because chip design workloads grow exponentially as chips become larger and more complex. He pointed to the industry’s historical productivity gains—shifting from hundreds of engineers over years to far smaller teams over months—while saying tool usage continued to rise because customers kept increasing ambition and complexity.
Devgan also discussed Cadence’s ChipStack Super Agent, calling it a new product category aimed at automating earlier stages of chip creation. He said chip design uses languages such as RTL (register transfer language) and SystemVerilog, and that while Cadence has long automated much of the process after RTL is written, the company historically did not automate writing RTL or testbenches. With ChipStack, he said, Cadence can generate RTL and verification testbenches, using what he described as a “mental model and knowledge graph” approach to improve LLM usefulness in chip workflows.
On monetization, Devgan said Cadence expects a model that combines a base subscription with token-based usage, describing it as a well-established AI pricing model. He said the company aims for these offerings to be margin accretive over time.
IP momentum, chiplets, and advanced nodes
Devgan said Cadence’s IP business is on track for its third consecutive year of “very good growth,” and stressed that the company typically does not highlight performance unless it has been sustained. He attributed the IP momentum to a stronger team, improved products, and a broader portfolio—particularly at advanced nodes and in AI/high-performance computing.
He cited high-value IP areas including HBM, which he said came through an acquisition from Rambus, as well as DDR (organic), UCI, PCIe, and SerDes. Devgan also said expanding advanced-node foundry participation—including TSMC, Intel, Samsung, and Rapidus—has increased demand for IP as more platforms require validated, standard-based solutions.
On chiplets and more complex packaging approaches, Devgan said the trend supports both EDA and IP. As more customers build custom silicon, he said they use more EDA tools and often prefer to buy standard-based IP so they can focus engineering resources on differentiated components such as CPUs or AI blocks.
Hardware (Palladium), margins, China, and M&A profitability
Devgan said Cadence’s hardware business—particularly Palladium emulation—has posted record growth for six consecutive years, and he said he is “pretty bullish” on another record year. He described Palladium as a combined hardware-software system that functions as a “Boolean supercomputer” for logic verification, enabling customers to emulate chips far faster than general-purpose compute and to overlap hardware and software development before silicon is available.
On financial priorities, Devgan said Cadence evaluates growth and margins together and aims to improve profitability and EPS. He cited last year’s margin performance and described a goal to “crack 60” on a Rule of 40-style metric, emphasizing incremental margin performance and internal efficiency improvements aided by AI.
Regarding the Hexagon simulation acquisition, Devgan said businesses Cadence acquires are typically less profitable initially and that it generally takes about a year to improve profitability. He noted there would be some impact in the current year—primarily on the financing side, including dilution or debt—while stating he expects the deal to be accretive next year.
On China, Devgan said the region performed well despite turbulence in 2025, and that the current environment appears more stable than early 2025. He said Cadence expects China to grow this year, though he cautioned that predicting regional growth is difficult. He added that Cadence maintains a strong position in China for EDA and hardware, including Palladium, while noting that IP has historically been a smaller focus there due to Cadence’s emphasis on advanced-node and AI-related IP.
About Cadence Design Systems (NASDAQ:CDNS)
Cadence Design Systems, Inc (NASDAQ: CDNS) is a global provider of electronic design automation (EDA) software, hardware and intellectual property used to design and verify advanced semiconductor chips, systems-on-chip (SoCs), printed circuit boards (PCBs) and packaging. Headquartered in San Jose, California and founded in 1988, Cadence serves semiconductor companies, original equipment manufacturers and system designers across the globe, helping customers accelerate design cycles and manage the complexity of modern integrated systems.
The company’s offerings span software tools for digital, custom/analog and mixed-signal design, verification and signoff, as well as solutions for system-level modeling, thermal and signal integrity analysis, and PCB and package design.
